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Ακαδημαϊκό έτος 2011-2012

27/4/2012, 14.30

Embedded Systems: Dynamic Data Type Refinement Methodologies

Lazaros Papadopoulos

Abstract: In the last years, complex applications from various domains are implemented in embedded devices. These applications make extended use of the dynamic memory to store dynamically allocated data structures. The implementation of these data structures affects the performance and the memory usage of the embedded systems. Thus, I will present the Dynamic Data Structure Methodology for optimizing applications from various domains in terms of performance and energy consumption. Also, I will present an extension to this approach: the adaptation of the dynamic data structure implementations to the requirements of the embedded system at runtime.

5/4/2012, 13.00

A Digital Design Flow
Dimitris Mpekiaris

Abstract: The development of automated digital design flows has emerged as a topic of significant activity not οnly in industry, but also in academia. The industrial tools targeting the state-of-the-art CMOS technology platforms (ASIC) tend to close the gap between the standard-cell based and the custom design, in terms of performance and power. At the same time, the growing experience of academia in working with industrial flows aims to the development of customized tools.

These may be based on the commercial packages, in order either to adapt them to the target research context, or to exploit their potential to make a step towards the automation of the design flow process. The specific branch attracts the interest from both research and industrial parts, as long as it significantly eases the designer’s/reseacher’s work, while it saves production time and effort, which should be devoted to design rather than scripting/IT-related issues. The latter comprise an advantage for both people of industry and academia, as the ease of use may either accelerate the design of an IP product or reduce the time required for a complex search-space exploration.

In this work, we have developed a front-end ASIC digital design flow, based on GNU Makefiles, Bash shell and Tcl scripts, to automate the steps of generating a standard-cell based synthesis netlist, starting from an RTL (Verilog/VHDL) description. Each design flow step (e.g. synthesis, timing/power analysis, simulation) is performed with a single make, whereas the corresponding scripts are also automatically generated, to save time from the designer. The proposed flow, which is fully parameterized and adaptive to most Linux platforms supporting bash scripting, is currently presented in batch mode, but we are currently working on adding a GUI extension, so that the main design parameters are inserted into  a Tk form.


30/3/2012, 14.00

SoC design using Python to accelerate biomolecular network simulations for systems biology

Evangelos Logaras, PhD candidate, Department of Informatics and Telecommunications, University of Athens

Abstract: We will present an overview of a SoC design tool, called SysPy (System Python) that we are developing. Our tool exploits the strengths of the popular Python scripting language to boost the productivity of processor-centric SoC designs for FPGAs. The goal of our research  is  to provide a tool and a design flow that would assist the user to easily incorporate a processor IP core in a SoC design, while Python descriptions could also be used for specific components connected to the processor. SysPy can be used to efficiently handle the design of a SoC with processor IP cores, accelerators, peripherals and their software ecosystem, e.g. compilers, embedded operating systems etc. A Hardware Abstraction Layer (HAL) has also been developed as a Python interface software.

The HAL software gives to the user access to the available resources on the FPGA and the processor core, after system’s implementation. Using the HAL the user can initiate various processing tasks on the SoC, while large amount of data can be transferred between the SoC and a host PC.

Using the Leon processor core and  an application specific co-processor developed in our group, a complete SoC system has been designed using SysPy. The co-processor can be used to implement the well known Gillespie’s algorithms to stochastically simulate in hardware biomolecular networks  with thousands of reactions as needed in large scale system biology studies. The designed SoC delivers simulation performance that is more than 80 times higher than that of software tools used in system biology. SysPy can be very useful in heterogeneous SoC designs where high performance cores are connected with processor cores and use them as communication gateways to access external processing and storage resources.

6/3/2012, 11.00

Energy-efficient processors for Datacenters

Christoforos Kachris

Abstract: The power consumption of the current data centers is one of the most challenging issues in the current IT ecosystem. Therefore, more energy efficient processors, storage elements, switches and memories are required that will provide increased processing power with reduced energy consumption. Currently, almost all of the web servers are based on high performance x86 architectures but are not power optimized. A possible alternative that is recently investigated, mainly by the research community and start-up companies, is the use of processors that are currently targeting embedded devices (e.g ARM). This talk will present the main challenges in the current data centers and will present some interesting research direction for energy efficient data centers.

17/2/2012, 14.00

Smart PV module, reconfigurable connections of solar cells

Maro Baka

Abstract: A photovoltaic system (or PV system) is a system which converts sunlight into electricity. It consists of multiple components: PV modules and means of regulating and/or modifying the electrical output among others. The efficiency of the solar system is reduced during dynamic conditions caused by time-dependent effects, like shading. The modules which are widely used nowadays are uniform. The excitation of the module and the factors which affect the module’s operation though are normally non uniform (irradiation, temperature, humidity). The proposed topology of the module is reconfigurable, allowing different configurations to be applied at run-time. The goal is to form groups of cells within the module which work under similar operating conditions in order to avoid mismatch effects and to improve the overall efficiency of the module.

20/1/2012, 13.00

Run-time Management for Multi-core platfroms.
Iraklis Anagnostopoulos

Abstract: Future integrated systems will contain billion of transistors, composing tens to hundreds of IP cores. Modern embedded platforms take advantage of this manufacturing technology advancement and are moving from Multi-Processor Systems-on-Chip (MPSoC) towards Many-Core architectures employing high numbers of processing cores. Resource management is a key technology for the successful use of such computing platforms. The run-time resource management paradigm has become prominent recently because it can deal with the run-time dynamics of applications and platforms.
In this presentation I will show my latest research work on run-time management focusing on run-time mapping and DVFS techniques applied at run-time. Last but not least, I will try to set anchors with previous presentations provided by other members of the lab.

8/12/2011, 14.00

Τrading Fault-Masking with Performance Overhead for Reconfigurable Architectures
Kostas Siozios

Abstract: For many decades, computer architects have pursued one primary goal: performance. The even-faster transistors provided by Moore’s law were translated into remarkable gains in operation frequency and power consumption. However, the device-level size and architecture complexity impose several new challenges, including a decrease in dependability level due to physical failures. This makes crucial the usage of fault tolerance during system level design, not only for safety critical systems, but almost for the majority of architectures. Existing solutions to this problem are not sufficient since they are characterized as expensive in terms of delay, power consumption and silicon area. This presentation introduces a software-supported methodology based on game theory for selectively protecting only
resources with increased probability of failure due to aging phenomena. Experimental results prove the efficiency of applying such a focused fault tolerant, as it achieves comparable fault masking to relevant solutions, but with significant lower mitigation cost.

22/11/2011, 14.00

«Λογοδοσία μιας ζωής … παρελθόν, παρόν και προοπτικές»

Ass. Prof.

Dimitrios Soudris 

Abstract: Σκοπός της ομιλίας είναι να παρουσιαστεί μια γενική εικόνα της δουλειάς που έχει πραγματοποιηθεί

παλαιότερα αλλά και πρόσφατα, τις τρέχουσες εργασίες, καθώς επίσης ποιες προοπτικές, δυνατότητες και ρεαλιστικές

ελπίδες έχουμε για να προχωρήσουμε στα επόμενα βήματα.

8/11/2011, 14.00

Thermal optimization for micro-architectures through selective block replication
Dionisis Diamantopoulos

Abstract: Increased power densities result to higher on-chip temperatures, which in turn creates numerous problems tightly firmed to reliability issues. This problem is expected to become even more severe for deep-submicron technologies. In this paper, we propose a thermal-aware exploration framework at the micro-architecture level for temperature hotspots elimination through selective resource replication. Experimental results based on the LEON3 processor synthesized with a 45 nm technology library, shown that the proposed methodology leads to designs with fewer hotspots, while the maximal temperatures at these hotspots are also reduced. Specifically, temperature reduction of 17 Kelvin degrees is feasible, which leads to improvement against aging phenomena about 14%, with a controllable overhead in silicon area about 15%, as compared to conventional architecture design.

4/11/2011, 14.00

Mapping reliability mitigation techniques on the Intel Single-chip Cloud Computer

Dimitris Rodopoulos

Abstract: This presentation will be divided in two sections. The first outlines the Single-chip Cloud Computer platform of Intel and is meant to be a short tutorial of its architecture, capabilities and features for the audience. The second (and shorter) part of the presentation will illustrate how a technique for mitigating soft errors in the memory organization of real-time embedded systems is currently being mapped on this platform to demonstrate its usefulness in a high performance computing context.

18/10/2011, 14.00

Market-Based Resource Management
Alex Bartzas

Abstract: The transition to many-core systems and the run-time dynamics introduced by application dynamism and hardware reliability degradation significantly complicate run-time resource management. Existing techniques are focused on minimizing application deadline misses while loosely optimizing some hardware objective functions such as power consumption and hot-spots. In this presentation we propose a method for distributing resource management and allowing hardware resources to manage themselves, thus to extend their lifetime/availability. Resources are treated as independent agents that can evaluate their own condition at run-time and translate their processing capabilities into a single number. Jobs, on the other hand, are assigned a single number that represents their urgency to be executed. Run-time resource management then degenerates into matching the supply of and demand for processing power in a manner similar to a marketplace.

Ακαδημαϊκή χρονιά 2010-2011

8/7/2011, 14:00

Variability, reliability and other beasts…

Antonis Papanikolaou

Abstract: In this presentation we illustrate the sources of several variability and reliability phenomena as well as their impact on the electronic system level performance metrics. We will briefly go over a large class of analysis and mitigation approaches for these problems which are based on control theory concepts and have been developed together with IMEC.

15/6/2011, 11:00

Harry Sidiropoulos

27/5/2011, 11:00

FIFO and memory allocations on heterogeneous platforms

Giannis Koutras

Abstract: As heterogeneous platforms emerge, the problem of memory mapping plays a substantial role to the performance and efficiency of implementations. In the current context, memory mapping involves the placement of variables of a C program to the available memory and communication resources of the hardware platform.


Στάθης Σωτηρίου-Ξανθόπουλος

Ακαδημαϊκή χρονιά 2009-2010

13/3/2009, 11.00

Application-Specific Temperature Reduction Strategy for 2D and 3D NoCs